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Timing Analysis Tool

oshwhub-official2v1.1.5
(0)Apache-2.0
A PCB timing analysis tool supporting path delay calculation, Setup/Hold time analysis, timing diagram visualization, and Timing Budget output. Automatically analyzes signal nets between two components, calculates timing margins in real-time, and supports exporting timing diagrams in SVG/PNG/JPG formats.
Details
Changelog
Historical versions
Comments

Timing Analysis Tool

oshwhub-official2
(0)Apache-2.0
Details
Changelog
Historical versions
Comments

Timing Analysis Tool

A professional PCB timing diagram analysis extension for JLCEDA Professional Edition (EasyEDA Pro).

Features

Main Interface

Main Interface

Net Highlighting

Highlighting

Theme Toggle

Theme Toggle

This extension analyzes timing relationships between two components in your PCB design. By selecting source and destination components, it automatically analyzes the signal nets between them, calculates path delay and timing margin in real-time, and generates intuitive timing diagrams.

1. Component Selection Analysis

  • Select source and destination components
  • Automatically identify common nets between components
  • Display component info and net list

2. Timing Parameters

  • Clock frequency setting (1-1000 MHz)
  • Setup Time (Tsu) configuration
  • Hold Time (Th) configuration
  • Real-time timing margin calculation

3. Timing Diagram Visualization

  • Generate intuitive SVG timing diagrams
  • Display clock, data output, data input signals
  • Mark Launch/Capture timing points
  • Show Setup/Hold time windows
  • Show Tpd propagation delay
  • Show PASS/FAIL status

4. Net Highlighting

  • Auto-highlight selected nets during analysis
  • Mouse hover temporary highlighting
  • Auto-unhighlight on close

5. Export

  • Support SVG/PNG/JPG export
  • PNG/JPG at 3x resolution

6. Interface Themes

  • Dark theme
  • Light theme
  • Follow system theme

7. Interactive Features

  • Mouse wheel horizontal zoom
  • Mouse drag pan view
  • Ctrl+wheel vertical scroll
  • Search filter nets

Installation

  1. Open JLCEDA Professional Edition
  2. Go to Extensions → Extension Manager
  3. Import the .eext file

Usage

Step 1: Analyze

  1. Open a PCB document
  2. Click menu: Timing Analysis → Select Components to Analyze
  3. Select two components on the PCB (source → destination)

Step 2: Configure

In the settings dialog:

  • Set clock frequency
  • Set Setup Time and Hold Time
  • Check nets to analyze (supports search filter)

Step 3: View Results

  • Click "Calculate" to see timing results
  • View timing diagram and margin

Cancel Selection

Click Timing Analysis → Cancel Selection

Timing Parameters

ParameterDescription
Clock FrequencyClock signal frequency (MHz)
PeriodClock period (ns) = 1000/frequency
Setup Time (Tsu)Time signal must be stable before clock edge
Hold Time (Th)Time signal must be stable after clock edge
TpdPropagation delay from source to destination
MarginTpd - Tsu - Th, positive = PASS

Requirements

  • JLCEDA Professional Edition v3.0.0+
  • No other extension dependencies

License

Apache-2.0

1.1.5

新增

  1. 新增支持多语言

1.1.4

新增

  1. 将"周期"输入框改为"板厚"输入框(mm),自动转换显示为 mil
  2. 过孔补偿计算:每个网络的过孔数 × 板厚 × 39.37mil,统一单位后加入总长度计算

修复

  1. 计算结果中增加过孔补偿显示

变更

  1. 板厚默认值:1.6mm

1.1.3

新增

  1. 添加内置主题切换按钮(小圆球日月图标),移除菜单栏主题选项
  2. 添加时间轴网格和刻度线,缩放时保持线宽和文字大小不变
  3. 缩放增加最小比例限制(0.5)

优化

  1. 横向缩放改用原生滚动,保留以鼠标为中心的缩放功能
  2. 主题记忆功能优化,添加调试日志
  3. 网络全选逻辑优化:搜索结果下只选中搜索结果范围内的网络

修复

  1. 修复缩放时 Tsu/Th 文本拉伸问题
  2. 修复浅色主题下网络名背景框变深黑色的问题
  3. 统一滚动逻辑,拖拽左键/中键控制 scrollTop

1.1.2

变更

  1. 使用纯 ESLint 的代码格式化方式
  2. 打包时额外进行压缩,可以获得更小的扩展包

1.1.1

修复

  1. 修复网络列表闭包问题:悬停时所有网络高亮为最后一个的问题

  2. 临时高亮逻辑优化:仅未选中的网络支持悬停临时高亮,选中网络保持高亮直到取消选择

  3. 缩放逻辑优化:

    • 单滚轮:横向缩放(以鼠标为中心)
    • Ctrl+滚轮:上下滚动
    • Shift+滚轮:左右滚动
    • 鼠标中键拖拽:全方位拖拽

1.1.0

新增

  1. 新增导出SVG功能,可将时序图导出为SVG文件

变更

  1. 优化按钮布局,导出按钮独立一行
  2. 删除Timing Summary框,简化时序图显示
  3. 优化时序参数设置界面,网络列表框加长显示
  4. 优化实时计算逻辑:参数变化时后台计算,点击"计算"按钮才更新显示
  5. 时序图UI重构:信号名称独立到左侧列,标题独立到上方,均不参与缩放
  6. 缩放逻辑修改:Ctrl+滚轮水平缩放,滚轮垂直滚动
  7. 优化信号名称与波形对应关系,同一信号紧凑排列
  8. 消除时序图左侧空白区域

1.0.0

初始版本

暂无数据
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Type

Other

Keyword

Timing时序延迟Signal IntegritySetupHoldTpdPCB

Extension Info

Versionv1.1.5
Author

oshwhub-official

Published at2026-06-26 09:34:39
Name

timing-analysis

UUID

5d7e348eb4624b129ca3502f20d308f4

Works with^3.0.0
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